The invention relates to a method for forming a semiconductor and, more particularly, to a method for forming patterns in a semiconductor memory device using a spacer.
As semiconductor devices have become more highly integrated, the semiconductor devices require resolution higher than that of the photolithography apparatus used to make patterns. For example, whereas the minimum size resolvable through a single exposure using the photolithography apparatus is 45 nm, a semiconductor device may require resolution smaller than 40 nm. Therefore, in order to overcome the limitation of the photolithography apparatus in forming ultra-fine patterns, a variety of methods have been suggested. One of them is a method for forming patterns using a spacer.
The method for forming patterns using a spacer includes forming a material layer pattern of a predetermined size on an etch target layer, forming a spacer around the material layer pattern, and etching the etch target layer using the spacer as an etch mask. As such, it is possible to form a pattern which is about as fine as the thickness of the spacer.
Accordingly, this method for forming patterns using a spacer is widely used to form patterns in highly integrated semiconductor memory devices.
However, since the spacers are formed to the same thickness independent of location, it is difficult to form repeated fine patterns such as lines/spaces and patterns greater than a predetermined size simultaneously with a single mask. Accordingly, a process for forming repeated fine patterns and a process for forming a pattern greater than a predetermined size should be performed separately with different masks. Therefore misalignment between the masks is likely to occur. In other words, when the patterns of different sizes are formed by the method for forming patterns using a spacer, misalignment may occur due to the different masks, which may cause partially different pattern spacings.
Such partially different pattern spacing may cause serious problems in a device such as a flash memory device where the spacing between the patterns has a significant effect on device characteristics. Spacing between a source select transistor and its adjacent word line, and spacing between a drain select transistor and its adjacent word line has the most significant effect on characteristics of the flash memory device. If these spacings are not uniform and do not satisfy critical dimensions (CDs), serious problems such as a program disturbance may occur in an operation of a device, and then the device cannot operate normally.
FIG. 1 illustrates a cross-sectional view of a semiconductor memory device with misaligned patterns formed by a typical method for forming patterns using a spacer.
Referring to FIG. 1, a spacing between a gate 110 of a drain select transistor and a gate 130 of a cell transistor adjacent to the drain select transistor, and a spacing between a gate 120 of a drain select transistor and a gate 132 of a cell transistor adjacent tot the drain select transistor in adjacent block do not match each other. In this case, a serious problem may occur during the operation of the device, and thus reliability of the device may be reduced. Such problems also occur frequently in other memory devices where spacing between patterns has significant effect on the device characteristics.